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@ -34,7 +34,7 @@
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#define CRYPTOPP_BOOL_ARM32 1
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#define CRYPTOPP_BOOL_ARM32 1
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#endif
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#endif
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// AltiVec and Power8 crypto
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// And PowerPC.
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#if defined(__ppc64__) || defined(__powerpc64__) || defined(__PPC64__) || defined(_ARCH_PPC64)
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#if defined(__ppc64__) || defined(__powerpc64__) || defined(__PPC64__) || defined(_ARCH_PPC64)
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#define CRYPTOPP_BOOL_PPC64 1
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#define CRYPTOPP_BOOL_PPC64 1
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#elif defined(__powerpc__) || defined(__ppc__) || defined(__PPC__) || defined(_ARCH_PPC)
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#elif defined(__powerpc__) || defined(__ppc__) || defined(__PPC__) || defined(_ARCH_PPC)
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@ -58,9 +58,8 @@
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// This should be a lower bound on the L1 cache line size.
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// This should be a lower bound on the L1 cache line size.
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// It's used for defense against timing attacks.
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// It's used for defense against timing attacks.
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#ifndef CRYPTOPP_L1_CACHE_LINE_SIZE
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#ifndef CRYPTOPP_L1_CACHE_LINE_SIZE
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#if defined(CRYPTOPP_BOOL_X32) || defined(CRYPTOPP_BOOL_X64) || \
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#if defined(CRYPTOPP_BOOL_X32) || defined(CRYPTOPP_BOOL_X64) || defined(CRYPTOPP_BOOL_ARMV8) || \
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defined(CRYPTOPP_BOOL_ARMV8) || defined(CRYPTOPP_BOOL_PPC64) || \
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defined(CRYPTOPP_BOOL_PPC64) || defined(CRYPTOPP_BOOL_MIPS64) || defined(CRYPTOPP_BOOL_SPARC64)
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defined(CRYPTOPP_BOOL_MIPS64) || defined(CRYPTOPP_BOOL_SPARC64)
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#define CRYPTOPP_L1_CACHE_LINE_SIZE 64
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#define CRYPTOPP_L1_CACHE_LINE_SIZE 64
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#else
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#else
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// L1 cache line size is 32 on Pentium III and earlier
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// L1 cache line size is 32 on Pentium III and earlier
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@ -91,6 +90,7 @@
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#define CRYPTOPP_NO_CPU_FEATURE_PROBES 1
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#define CRYPTOPP_NO_CPU_FEATURE_PROBES 1
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#endif
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#endif
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// Flavor of inline assembly language
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#if defined(_MSC_VER) || defined(__BORLANDC__)
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#if defined(_MSC_VER) || defined(__BORLANDC__)
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#define CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY 1
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#define CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY 1
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#else
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#else
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