Updated documentation
Jeffrey Walton
parent
34e95a7cde
commit
66ada4cc61
67
cpu.h
67
cpu.h
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@ -2,9 +2,7 @@
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//! \file cpu.h
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//! \brief Functions for CPU features and intrinsics
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//! \details At the moment, the functions are used heavily in X86/X32/X64 code paths
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// for SSE, SSE2 and SSE4. The funtions are also used on occassion for AArch32
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//! and AArch64 code paths for NEON.
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//! \details The functions are used in X86/X32/X64 and NEON code paths
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#ifndef CRYPTOPP_CPU_H
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#define CRYPTOPP_CPU_H
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@ -141,11 +139,13 @@ NAMESPACE_END
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NAMESPACE_BEGIN(CryptoPP)
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#if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
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#if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_DOXYGEN_PROCESSING
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#define CRYPTOPP_CPUID_AVAILABLE
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// these should not be used directly
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// Hide from Doxygen
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#ifndef CRYPTOPP_DOXYGEN_PROCESSING
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// These should not be used directly
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extern CRYPTOPP_DLL bool g_x86DetectionDone;
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extern CRYPTOPP_DLL bool g_hasMMX;
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extern CRYPTOPP_DLL bool g_hasISSE;
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@ -166,7 +166,12 @@ extern CRYPTOPP_DLL word32 g_cacheLineSize;
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CRYPTOPP_DLL void CRYPTOPP_API DetectX86Features();
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CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 input, word32 output[4]);
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#endif // CRYPTOPP_DOXYGEN_PROCESSING
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//! \brief Determines MMX availability
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//! \returns true if MMX is determined to be available, false otherwise
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//! \details MMX, SSE and SSE2 are core processor features for x86_64, and
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//! the function always returns true for the platform.
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inline bool HasMMX()
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{
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#if CRYPTOPP_BOOL_X64
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@ -178,6 +183,10 @@ inline bool HasMMX()
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#endif
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}
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//! \brief Determines SSE availability
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//! \returns true if SSE is determined to be available, false otherwise
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//! \details MMX, SSE and SSE2 are core processor features for x86_64, and
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//! the function always returns true for the platform.
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inline bool HasISSE()
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{
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#if CRYPTOPP_BOOL_X64
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@ -189,6 +198,10 @@ inline bool HasISSE()
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#endif
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}
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//! \brief Determines SSE2 availability
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//! \returns true if SSE2 is determined to be available, false otherwise
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//! \details MMX, SSE and SSE2 are core processor features for x86_64, and
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//! the function always returns true for the platform.
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inline bool HasSSE2()
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{
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#if CRYPTOPP_BOOL_X64
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@ -200,6 +213,10 @@ inline bool HasSSE2()
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#endif
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}
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//! \brief Determines SSSE3 availability
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//! \returns true if SSSE3 is determined to be available, false otherwise
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//! \details HasSSSE3() is a runtime check performed using CPUID
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//! \note Some Clang compilers incorrectly omit SSSE3 even though its native to the processor.
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inline bool HasSSSE3()
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{
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if (!g_x86DetectionDone)
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@ -207,6 +224,9 @@ inline bool HasSSSE3()
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return g_hasSSSE3;
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}
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//! \brief Determines SSE4 availability
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//! \returns true if SSE4.1 and SSE4.2 are determined to be available, false otherwise
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//! \details HasSSE4() is a runtime check performed using CPUID which requires both SSE4.1 and SSE4.2
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inline bool HasSSE4()
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{
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if (!g_x86DetectionDone)
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@ -214,6 +234,9 @@ inline bool HasSSE4()
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return g_hasSSE4;
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}
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//! \brief Determines AES-NI availability
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//! \returns true if AES-NI is determined to be available, false otherwise
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//! \details HasAESNI() is a runtime check performed using CPUID
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inline bool HasAESNI()
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{
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if (!g_x86DetectionDone)
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@ -221,6 +244,9 @@ inline bool HasAESNI()
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return g_hasAESNI;
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}
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//! \brief Determines Carryless Multiply availability
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//! \returns true if pclmulqdq is determined to be available, false otherwise
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//! \details HasCLMUL() is a runtime check performed using CPUID
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inline bool HasCLMUL()
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{
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if (!g_x86DetectionDone)
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@ -228,6 +254,9 @@ inline bool HasCLMUL()
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return g_hasCLMUL;
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}
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//! \brief Determines if the CPU is an Intel P4
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//! \returns true if the CPU is a P4, false otherwise
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//! \details IsP4() is a runtime check performed using CPUID
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inline bool IsP4()
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{
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if (!g_x86DetectionDone)
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@ -235,6 +264,9 @@ inline bool IsP4()
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return g_isP4;
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}
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//! \brief Determines RDRAND availability
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//! \returns true if RDRAND is determined to be available, false otherwise
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//! \details HasRDRAND() is a runtime check performed using CPUID
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inline bool HasRDRAND()
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{
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if (!g_x86DetectionDone)
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@ -242,6 +274,9 @@ inline bool HasRDRAND()
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return g_hasRDRAND;
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}
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//! \brief Determines RDSEED availability
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//! \returns true if RDSEED is determined to be available, false otherwise
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//! \details HasRDSEED() is a runtime check performed using CPUID
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inline bool HasRDSEED()
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{
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if (!g_x86DetectionDone)
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@ -249,6 +284,9 @@ inline bool HasRDSEED()
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return g_hasRDSEED;
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}
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//! \brief Determines Padlock RNG availability
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//! \returns true if VIA Padlock RNG is determined to be available, false otherwise
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//! \details HasPadlockRNG() is a runtime check performed using CPUID
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inline bool HasPadlockRNG()
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{
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if (!g_x86DetectionDone)
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@ -256,6 +294,9 @@ inline bool HasPadlockRNG()
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return g_hasPadlockRNG;
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}
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//! \brief Determines Padlock ACE availability
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//! \returns true if VIA Padlock ACE is determined to be available, false otherwise
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//! \details HasPadlockACE() is a runtime check performed using CPUID
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inline bool HasPadlockACE()
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{
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if (!g_x86DetectionDone)
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@ -263,6 +304,9 @@ inline bool HasPadlockACE()
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return g_hasPadlockACE;
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}
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//! \brief Determines Padlock ACE2 availability
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//! \returns true if VIA Padlock ACE2 is determined to be available, false otherwise
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//! \details HasPadlockACE2() is a runtime check performed using CPUID
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inline bool HasPadlockACE2()
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{
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if (!g_x86DetectionDone)
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@ -270,6 +314,9 @@ inline bool HasPadlockACE2()
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return g_hasPadlockACE2;
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}
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//! \brief Determines Padlock PHE availability
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//! \returns true if VIA Padlock PHE is determined to be available, false otherwise
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//! \details HasPadlockPHE() is a runtime check performed using CPUID
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inline bool HasPadlockPHE()
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{
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if (!g_x86DetectionDone)
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@ -277,6 +324,9 @@ inline bool HasPadlockPHE()
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return g_hasPadlockPHE;
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}
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//! \brief Determines Padlock PMM availability
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//! \returns true if VIA Padlock PMM is determined to be available, false otherwise
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//! \details HasPadlockPMM() is a runtime check performed using CPUID
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inline bool HasPadlockPMM()
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{
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if (!g_x86DetectionDone)
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return g_hasPadlockPMM;
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}
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//! \brief Provides the cache line size
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//! \returns lower bound on the size of a cache line in bytes, if available
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//! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
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//! is available. If the value is not available at runtime, then 32 is returned for a 32-bit
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//! processor and 64 is returned for a 64-bit processor.
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//! \details x86/x32/x64 uses CPUID to determine the value and its usually accurate. The ARM
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//! processor equivalent is a privileged instruction, so a compile time value is returned.
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inline int GetCacheLineSize()
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{
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if (!g_x86DetectionDone)
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