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Use fallback in detecting ARM and PowerPC cache line size

pull/838/head
Jeffrey Walton 2019-05-08 19:54:05 -04:00
parent c91813c0b4
commit 72a71eb230
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GPG Key ID: B36AB348921B1838
1 changed files with 16 additions and 10 deletions
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26
cpu.cpp
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@ -458,16 +458,16 @@ void DetectX86Features()
CpuId(0xC0000005, 0, cpuid2); CpuId(0xC0000005, 0, cpuid2);
g_cacheLineSize = GETBYTE(cpuid2[2] /*ECX*/, 0); g_cacheLineSize = GETBYTE(cpuid2[2] /*ECX*/, 0);
} }
#if defined(_SC_LEVEL1_DCACHE_LINESIZE)
else
{
int cacheLineSize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
if (cacheLineSize > 0)
g_cacheLineSize = cacheLineSize;
}
#endif
} }
#if defined(_SC_LEVEL1_DCACHE_LINESIZE)
// Glibc does not implement on some platforms. The runtime returns 0 instead of error.
// https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/posix/sysconf.c
int cacheLineSize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
if (cacheLineSize > 0)
g_cacheLineSize = cacheLineSize;
#endif
if (g_cacheLineSize == 0) if (g_cacheLineSize == 0)
g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE; g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
@ -849,7 +849,7 @@ void DetectArmFeatures()
g_hasSM3 = CPU_QuerySM3(); // || CPU_ProbeSM3(); g_hasSM3 = CPU_QuerySM3(); // || CPU_ProbeSM3();
g_hasSM4 = CPU_QuerySM4(); // || CPU_ProbeSM4(); g_hasSM4 = CPU_QuerySM4(); // || CPU_ProbeSM4();
#if defined(__linux__) && defined(_SC_LEVEL1_DCACHE_LINESIZE) #if defined(_SC_LEVEL1_DCACHE_LINESIZE)
// Glibc does not implement on some platforms. The runtime returns 0 instead of error. // Glibc does not implement on some platforms. The runtime returns 0 instead of error.
// https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/posix/sysconf.c // https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/posix/sysconf.c
int cacheLineSize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE); int cacheLineSize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
@ -857,6 +857,9 @@ void DetectArmFeatures()
g_cacheLineSize = cacheLineSize; g_cacheLineSize = cacheLineSize;
#endif #endif
if (g_cacheLineSize == 0)
g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
*const_cast<volatile bool*>(&g_ArmDetectionDone) = true; *const_cast<volatile bool*>(&g_ArmDetectionDone) = true;
} }
@ -1066,7 +1069,7 @@ void DetectPowerpcFeatures()
int cacheLineSize = getsystemcfg(SC_L1C_DLS); int cacheLineSize = getsystemcfg(SC_L1C_DLS);
if (cacheLineSize > 0) if (cacheLineSize > 0)
g_cacheLineSize = cacheLineSize; g_cacheLineSize = cacheLineSize;
#elif defined(__linux__) && defined(_SC_LEVEL1_DCACHE_LINESIZE) #elif defined(_SC_LEVEL1_DCACHE_LINESIZE)
// Glibc does not implement on some platforms. The runtime returns 0 instead of error. // Glibc does not implement on some platforms. The runtime returns 0 instead of error.
// https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/posix/sysconf.c // https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/posix/sysconf.c
int cacheLineSize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE); int cacheLineSize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
@ -1074,6 +1077,9 @@ void DetectPowerpcFeatures()
g_cacheLineSize = cacheLineSize; g_cacheLineSize = cacheLineSize;
#endif #endif
if (g_cacheLineSize == 0)
g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
*const_cast<volatile bool*>(&g_PowerpcDetectionDone) = true; *const_cast<volatile bool*>(&g_PowerpcDetectionDone) = true;
} }