diff --git a/cpu.h b/cpu.h
index 8b8e72c3..9e2b7572 100644
--- a/cpu.h
+++ b/cpu.h
@@ -255,8 +255,9 @@ inline bool HasPadlockPMM()
 //! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
 //!   is available. If the value is not available at runtime, then 32 is returned for a 32-bit
 //!   processor and 64 is returned for a 64-bit processor.
-//! \details x86/x32/x64 uses CPUID to determine the value and its usually accurate. The ARM
-//!   processor equivalent is a privileged instruction, so a compile time value is returned.
+//! \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC
+//!   and AIX also makes the value available to user space and it is also usually accurate. The
+//!   ARM processor equivalent is a privileged instruction, so a compile time value is returned.
 inline int GetCacheLineSize()
 {
 	if (!g_x86DetectionDone)
@@ -416,12 +417,12 @@ inline bool HasAltivec()
 	return g_hasAltivec;
 }
 
-//! \brief Determine if a PowerPC processor has Power7 available
-//! \returns true if the hardware is capable of Power7 at runtime, false otherwise.
+//! \brief Determine if a PowerPC processor has Power8 available
+//! \returns true if the hardware is capable of Power8 at runtime, false otherwise.
 //! \details Altivec instructions are available under most modern PowerPCs.
 //! \details Runtime support requires compile time support. When compiling with GCC, you may
-//!   need to compile with <tt>-mcpu=power7</tt>; while IBM XL C/C++ compilers require
-//!   <tt>-qarch=pwr7 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
+//!   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
+//!   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
 //! \note This function is only available on PowerPC and PowerPC-64 platforms
 inline bool HasPower8()
 {
@@ -444,9 +445,9 @@ inline bool HasAES()
 	return g_hasAES;
 }
 
-//! \brief Determine if a PowerPC processor has AES available
-//! \returns true if the hardware is capable of AES at runtime, false otherwise.
-//! \details AES is part of the in-crypto extensions on Power8 and Power9.
+//! \brief Determine if a PowerPC processor has SHA1 available
+//! \returns true if the hardware is capable of SHA1 at runtime, false otherwise.
+//! \details SHA is part of the in-crypto extensions on Power8 and Power9.
 //! \details Runtime support requires compile time support. When compiling with GCC, you may
 //!   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
 //!   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
@@ -458,9 +459,9 @@ inline bool HasSHA1()
 	return g_hasSHA1;
 }
 
-//! \brief Determine if a PowerPC processor has AES available
-//! \returns true if the hardware is capable of AES at runtime, false otherwise.
-//! \details AES is part of the in-crypto extensions on Power8 and Power9.
+//! \brief Determine if a PowerPC processor has SHA2 available
+//! \returns true if the hardware is capable of SHA2 at runtime, false otherwise.
+//! \details SHA is part of the in-crypto extensions on Power8 and Power9.
 //! \details Runtime support requires compile time support. When compiling with GCC, you may
 //!   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
 //!   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
@@ -477,8 +478,9 @@ inline bool HasSHA2()
 //! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
 //!   is available. If the value is not available at runtime, then 32 is returned for a 32-bit
 //!   processor and 64 is returned for a 64-bit processor.
-//! \details x86/x32/x64 uses CPUID to determine the value and its usually accurate. The ARM
-//!   processor equivalent is a privileged instruction, so a compile time value is returned.
+//! \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC
+//!   and AIX also makes the value available to user space and it is also usually accurate. The
+//!   ARM processor equivalent is a privileged instruction, so a compile time value is returned.
 inline int GetCacheLineSize()
 {
 	if (!g_PowerpcDetectionDone)
@@ -492,10 +494,14 @@ inline int GetCacheLineSize()
 
 // Non-Intel systems
 #if !(CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64)
-//! \brief Provides the cache line size at runtime
-//! \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
-//! \details GetCacheLineSize() provides is an estimate using CRYPTOPP_L1_CACHE_LINE_SIZE.
-//!   The runtime instructions to query the processor are privileged.
+//! \brief Provides the cache line size
+//! \returns lower bound on the size of a cache line in bytes, if available
+//! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
+//!   is available. If the value is not available at runtime, then 32 is returned for a 32-bit
+//!   processor and 64 is returned for a 64-bit processor.
+//! \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC
+//!   and AIX also makes the value available to user space and it is also usually accurate. The
+//!   ARM processor equivalent is a privileged instruction, so a compile time value is returned.
 inline int GetCacheLineSize()
 {
 	return CRYPTOPP_L1_CACHE_LINE_SIZE;