adea69ab68
Avoid increment during stores of 6x blocks
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This provides another 0.1 cpb with GCC
2017-09-14 21:06:44 -04:00
25efb7a140
Use 6x blocks for ARMv8 AES rather than 4x
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We gain 0.1 to 0.3 cpb, depending on the mode
2017-09-14 20:32:06 -04:00
58890ff053
Use 6x blocks for Power8 AES rather than 4x
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Perforamnce increased for all modes when performing 6x vs 4x. 8x and 12x performed worse.
Here are the numbers:
4x Blocks:
<TR><TH>AES/CTR (128-bit key)<TD>1563<TD>2.1<TD>0.409<TD>1392
<TR><TH>AES/CTR (192-bit key)<TD>1403<TD>2.3<TD>0.450<TD>1529
<TR><TH>AES/CTR (256-bit key)<TD>1280<TD>2.5<TD>0.482<TD>1639
<TR><TH>AES/CBC (128-bit key)<TD>582<TD>5.6<TD>0.359<TD>1222
<TR><TH>AES/CBC (192-bit key)<TD>517<TD>6.3<TD>0.394<TD>1339
<TR><TH>AES/CBC (256-bit key)<TD>474<TD>6.8<TD>0.432<TD>1469
<TR><TH>AES/OFB (128-bit key)<TD>533<TD>6.1<TD>0.402<TD>1368
<TR><TH>AES/CFB (128-bit key)<TD>563<TD>5.8<TD>0.461<TD>1568
<TR><TH>AES/ECB (128-bit key)<TD>1829<TD>1.8<TD>0.240<TD>817
6x Blocks:
<TR><TH>AES/CTR (128-bit key)<TD>1750<TD>1.7<TD>0.406<TD>1300
<TR><TH>AES/CTR (192-bit key)<TD>1638<TD>1.9<TD>0.447<TD>1432
<TR><TH>AES/CTR (256-bit key)<TD>1528<TD>2.0<TD>0.482<TD>1541
<TR><TH>AES/CBC (128-bit key)<TD>582<TD>5.2<TD>0.358<TD>1145
<TR><TH>AES/CBC (192-bit key)<TD>517<TD>5.9<TD>0.394<TD>1260
<TR><TH>AES/CBC (256-bit key)<TD>474<TD>6.4<TD>0.431<TD>1379
<TR><TH>AES/OFB (128-bit key)<TD>533<TD>5.7<TD>0.400<TD>1281
<TR><TH>AES/CFB (128-bit key)<TD>563<TD>5.4<TD>0.461<TD>1476
<TR><TH>AES/ECB (128-bit key)<TD>1950<TD>1.6<TD>0.238<TD>763
2017-09-14 16:07:21 -04:00
08e4ee422e
Avoid increment during stores of 4x blocks
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This provides another 0.1 cpb with GCC
2017-09-14 15:12:07 -04:00
ddeae859d0
Use vec_xl_be and vec_xst_be for IBM XL C/C++ compiler
2017-09-14 13:27:49 -04:00
63a0af4efa
Fix endianess for s_one on ARM big-endian
2017-09-13 22:52:29 -04:00
8e52ce6dd2
Load correct value fo 1 under ARM big endian
2017-09-13 21:42:15 -04:00
c22507e38b
Clear unused variable warnings under Clang
2017-09-13 21:37:55 -04:00
8d98417306
Add Aarch64 specific defines to Android cross-compile
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Move <arm_acle.h> logic into "sonfig.h". Detecting when we can/should include <arm_acle.h> is proving to be troublesome
2017-09-13 17:16:57 -04:00
397ccd7e49
remove commented code for Power8
2017-09-13 03:59:25 -04:00
2b24f5b9fe
VectorLoadAligned → VectorLoadKey
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Add comments for the Load and Store functions
2017-09-12 20:38:58 -04:00
5659acb704
Cleanup vector casts
2017-09-12 19:44:34 -04:00
6899d3f8bb
Add AdvancedProcessBlocks for Power8
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This increases performance to about 1.6 cpb. We are about 0.5 cpb behind Botan, and about 1.0 cpb behind OpenSSL. However, it beats the snot out of C/C++, which runs at 20 to 30 cpb
2017-09-12 18:15:55 -04:00
b090e5f69f
Add Power8 AES decryption
2017-09-12 05:53:17 -04:00
7fb34e9b08
Add Power8 AES encryption
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This is the forward direction on encryption only. Crypto++ uses the "Equivalent Inverse Cipher" (FIPS-197, Section 5.3.5, p.23), and it is not compatible with IBM hardware. The library library will need to re-work the decryption key scheduling routines. (We may be able to work around it another way, but I have not investigated it).
2017-09-11 22:52:22 -04:00
37e02f9e0e
Revert AltiVec and Power8 commits
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The strategy of "cleanup under-aligned buffers" is not scaling well. Corner cases are still turing up. The library has some corner-case breaks, like old 32-bit Intels. And it still has not solved the AltiVec and Power8 alignment problems.
For now we are backing out the changes and investigating other strategies
2017-09-05 16:28:00 -04:00
75aef9bded
Fixup under-aligned buffers when using AES on AltiVec and Power8
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This commit supports the upcoming AltiVec and Power8 processor. This commit affects a number of classes due to the ubiquitous use of AES. The commit provides the data alignment requirements.
2017-09-04 11:21:47 -04:00
5c6a32ba0f
Support Base Implementation + SIMD implementation on Solaris (PR #461 )
2017-08-24 19:17:21 -04:00
a19f0c663b
Update asserts
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Change 'rounds' to size_t in Rijndael_AdvancedProcessBlocks_ARMV8
2017-08-19 01:55:20 -04:00
a1b3102eab
Update comments
2017-08-19 01:35:36 -04:00
51fe8a7776
Guard use of SIGILL probes on Apple platforms
2017-08-17 18:06:57 -04:00
e2c377effd
Split source files to support Base Implementation + SIMD implementation (GH #461 )
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Split source files to support Base Implementation + SIMD implementation
2017-08-17 12:33:43 -04:00
Jeffrey Walton