376 lines
10 KiB
C++
376 lines
10 KiB
C++
// cpu.cpp - originally written and placed in the public domain by Wei Dai
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#include "pch.h"
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#include "config.h"
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#ifndef EXCEPTION_EXECUTE_HANDLER
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# define EXCEPTION_EXECUTE_HANDLER 1
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#endif
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#ifndef CRYPTOPP_IMPORTS
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#include "cpu.h"
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#include "misc.h"
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#include "stdcpp.h"
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#ifdef CRYPTOPP_GNU_STYLE_INLINE_ASSEMBLY
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#include <signal.h>
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#include <setjmp.h>
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#endif
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NAMESPACE_BEGIN(CryptoPP)
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#ifndef CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
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extern "C" {
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typedef void (*SigHandler)(int);
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};
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#endif // Not CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
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#ifdef CRYPTOPP_CPUID_AVAILABLE
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#if _MSC_VER >= 1400 && CRYPTOPP_BOOL_X64
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bool CpuId(word32 input, word32 output[4])
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{
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__cpuid((int *)output, input);
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return true;
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}
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#else
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#ifndef CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
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extern "C"
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{
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static jmp_buf s_jmpNoCPUID;
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static void SigIllHandlerCPUID(int)
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{
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longjmp(s_jmpNoCPUID, 1);
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}
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static jmp_buf s_jmpNoSSE2;
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static void SigIllHandlerSSE2(int)
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{
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longjmp(s_jmpNoSSE2, 1);
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}
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}
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#endif
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bool CpuId(word32 input, word32 output[4])
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{
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#if defined(CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY)
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__try
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{
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__asm
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{
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mov eax, input
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mov ecx, 0
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cpuid
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mov edi, output
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mov [edi], eax
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mov [edi+4], ebx
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mov [edi+8], ecx
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mov [edi+12], edx
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}
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}
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// GetExceptionCode() == EXCEPTION_ILLEGAL_INSTRUCTION
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__except (EXCEPTION_EXECUTE_HANDLER)
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{
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return false;
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}
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// function 0 returns the highest basic function understood in EAX
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if(input == 0)
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return !!output[0];
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return true;
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#else
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// longjmp and clobber warnings. Volatile is required.
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// http://github.com/weidai11/cryptopp/issues/24 and http://stackoverflow.com/q/7721854
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volatile bool result = true;
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volatile SigHandler oldHandler = signal(SIGILL, SigIllHandlerCPUID);
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if (oldHandler == SIG_ERR)
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return false;
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# ifndef __MINGW32__
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volatile sigset_t oldMask;
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if (sigprocmask(0, NULLPTR, (sigset_t*)&oldMask))
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return false;
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# endif
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if (setjmp(s_jmpNoCPUID))
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result = false;
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else
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{
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asm volatile
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(
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// save ebx in case -fPIC is being used
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// TODO: this might need an early clobber on EDI.
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# if CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
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"pushq %%rbx; cpuid; mov %%ebx, %%edi; popq %%rbx"
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# else
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"push %%ebx; cpuid; mov %%ebx, %%edi; pop %%ebx"
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# endif
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: "=a" (output[0]), "=D" (output[1]), "=c" (output[2]), "=d" (output[3])
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: "a" (input), "c" (0)
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: "cc"
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);
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}
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# ifndef __MINGW32__
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sigprocmask(SIG_SETMASK, (sigset_t*)&oldMask, NULLPTR);
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# endif
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signal(SIGILL, oldHandler);
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return result;
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#endif
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}
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#endif
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static bool TrySSE2()
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{
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#if CRYPTOPP_BOOL_X64
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return true;
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#elif defined(CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY)
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__try
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{
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#if CRYPTOPP_BOOL_SSE2_ASM_AVAILABLE
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AS2(por xmm0, xmm0) // executing SSE2 instruction
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#elif CRYPTOPP_SSE2_AVAILABLE
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__m128i x = _mm_setzero_si128();
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return _mm_cvtsi128_si32(x) == 0;
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#endif
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}
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// GetExceptionCode() == EXCEPTION_ILLEGAL_INSTRUCTION
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__except (EXCEPTION_EXECUTE_HANDLER)
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{
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return false;
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}
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return true;
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#else
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// longjmp and clobber warnings. Volatile is required.
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// http://github.com/weidai11/cryptopp/issues/24 and http://stackoverflow.com/q/7721854
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volatile bool result = true;
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volatile SigHandler oldHandler = signal(SIGILL, SigIllHandlerSSE2);
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if (oldHandler == SIG_ERR)
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return false;
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# ifndef __MINGW32__
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volatile sigset_t oldMask;
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if (sigprocmask(0, NULLPTR, (sigset_t*)&oldMask))
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return false;
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# endif
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if (setjmp(s_jmpNoSSE2))
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result = false;
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else
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{
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#if CRYPTOPP_BOOL_SSE2_ASM_AVAILABLE
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__asm __volatile ("por %xmm0, %xmm0");
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#elif CRYPTOPP_SSE2_AVAILABLE
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__m128i x = _mm_setzero_si128();
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result = _mm_cvtsi128_si32(x) == 0;
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#endif
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}
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# ifndef __MINGW32__
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sigprocmask(SIG_SETMASK, (sigset_t*)&oldMask, NULLPTR);
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# endif
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signal(SIGILL, oldHandler);
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return result;
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#endif
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}
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bool CRYPTOPP_SECTION_INIT g_x86DetectionDone = false;
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bool CRYPTOPP_SECTION_INIT CRYPTOPP_SECTION_INIT g_hasSSE2 = false, CRYPTOPP_SECTION_INIT g_hasSSSE3 = false;
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bool CRYPTOPP_SECTION_INIT g_hasSSE41 = false, CRYPTOPP_SECTION_INIT g_hasSSE42 = false;
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bool CRYPTOPP_SECTION_INIT g_hasAESNI = false, CRYPTOPP_SECTION_INIT g_hasCLMUL = false, CRYPTOPP_SECTION_INIT g_hasSHA = false;
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bool CRYPTOPP_SECTION_INIT g_hasRDRAND = false, CRYPTOPP_SECTION_INIT g_hasRDSEED = false, CRYPTOPP_SECTION_INIT g_isP4 = false;
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bool CRYPTOPP_SECTION_INIT g_hasPadlockRNG = false, CRYPTOPP_SECTION_INIT g_hasPadlockACE = false, CRYPTOPP_SECTION_INIT g_hasPadlockACE2 = false;
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bool CRYPTOPP_SECTION_INIT g_hasPadlockPHE = false, CRYPTOPP_SECTION_INIT g_hasPadlockPMM = false;
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word32 CRYPTOPP_SECTION_INIT g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
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static inline bool IsIntel(const word32 output[4])
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{
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// This is the "GenuineIntel" string
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return (output[1] /*EBX*/ == 0x756e6547) &&
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(output[2] /*ECX*/ == 0x6c65746e) &&
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(output[3] /*EDX*/ == 0x49656e69);
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}
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static inline bool IsAMD(const word32 output[4])
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{
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// This is the "AuthenticAMD" string. Some early K5's can return "AMDisbetter!"
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return (output[1] /*EBX*/ == 0x68747541) &&
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(output[2] /*ECX*/ == 0x444D4163) &&
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(output[3] /*EDX*/ == 0x69746E65);
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}
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static inline bool IsVIA(const word32 output[4])
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{
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// This is the "CentaurHauls" string. Some non-PadLock's can return "VIA VIA VIA "
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return (output[1] /*EBX*/ == 0x746e6543) &&
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(output[2] /*ECX*/ == 0x736c7561) &&
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(output[3] /*EDX*/ == 0x48727561);
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}
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void DetectX86Features()
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{
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// Coverity finding CID 171239...
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word32 cpuid1[4]={0}, cpuid2[4]={0}, cpuid3[4]={0};
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if (!CpuId(0, cpuid1))
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return;
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if (!CpuId(1, cpuid2))
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return;
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if ((cpuid2[3] & (1 << 26)) != 0)
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g_hasSSE2 = TrySSE2();
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g_hasSSSE3 = g_hasSSE2 && (cpuid2[2] & (1<<9));
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g_hasSSE41 = g_hasSSE2 && (cpuid2[2] & (1<<19));
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g_hasSSE42 = g_hasSSE2 && (cpuid2[2] & (1<<20));
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g_hasAESNI = g_hasSSE2 && (cpuid2[2] & (1<<25));
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g_hasCLMUL = g_hasSSE2 && (cpuid2[2] & (1<<1));
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if (IsIntel(cpuid1))
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{
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static const unsigned int RDRAND_FLAG = (1 << 30);
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static const unsigned int RDSEED_FLAG = (1 << 18);
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static const unsigned int SHA_FLAG = (1 << 29);
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g_isP4 = ((cpuid2[0] >> 8) & 0xf) == 0xf;
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g_cacheLineSize = 8 * GETBYTE(cpuid2[1], 1);
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g_hasRDRAND = !!(cpuid2[2] /*ECX*/ & RDRAND_FLAG);
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if (cpuid1[0] /*EAX*/ >= 7)
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{
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if (CpuId(7, cpuid3))
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{
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g_hasRDSEED = !!(cpuid3[1] /*EBX*/ & RDSEED_FLAG);
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g_hasSHA = !!(cpuid3[1] /*EBX*/ & SHA_FLAG);
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}
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}
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}
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else if (IsAMD(cpuid1))
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{
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static const unsigned int RDRAND_FLAG = (1 << 30);
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static const unsigned int RDSEED_FLAG = (1 << 18);
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static const unsigned int SHA_FLAG = (1 << 29);
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CpuId(0x01, cpuid1);
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g_hasRDRAND = !!(cpuid1[2] /*ECX*/ & RDRAND_FLAG);
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if (cpuid1[0] /*EAX*/ >= 7)
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{
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if (CpuId(7, cpuid3))
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{
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g_hasRDSEED = !!(cpuid3[1] /*EBX*/ & RDSEED_FLAG);
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g_hasSHA = !!(cpuid3[1] /*EBX*/ & SHA_FLAG);
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}
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}
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CpuId(0x80000005, cpuid1);
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g_cacheLineSize = GETBYTE(cpuid1[2], 0);
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}
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else if (IsVIA(cpuid1))
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{
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static const unsigned int RNG_FLAGS = (0x3 << 2);
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static const unsigned int ACE_FLAGS = (0x3 << 6);
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static const unsigned int ACE2_FLAGS = (0x3 << 8);
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static const unsigned int PHE_FLAGS = (0x3 << 10);
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static const unsigned int PMM_FLAGS = (0x3 << 12);
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CpuId(0xC0000000, cpuid1);
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if (cpuid1[0] >= 0xC0000001)
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{
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// Extended features available
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CpuId(0xC0000001, cpuid1);
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g_hasPadlockRNG = !!(cpuid1[3] /*EDX*/ & RNG_FLAGS);
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g_hasPadlockACE = !!(cpuid1[3] /*EDX*/ & ACE_FLAGS);
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g_hasPadlockACE2 = !!(cpuid1[3] /*EDX*/ & ACE2_FLAGS);
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g_hasPadlockPHE = !!(cpuid1[3] /*EDX*/ & PHE_FLAGS);
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g_hasPadlockPMM = !!(cpuid1[3] /*EDX*/ & PMM_FLAGS);
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}
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}
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if (!g_cacheLineSize)
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g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
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g_x86DetectionDone = true;
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}
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#elif (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64)
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// The ARM equivalent of CPUID probing is reading a MSR. The code requires Exception Level 1 (EL1)
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// and above, but user space runs at EL0. Attempting to run the code results in a SIGILL and termination.
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//
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// #if defined(__arm64__) || defined(__aarch64__)
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// word64 caps = 0; // Read ID_AA64ISAR0_EL1
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// __asm __volatile("mrs %0, " "id_aa64isar0_el1" : "=r" (caps));
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// #elif defined(__arm__) || defined(__aarch32__)
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// word32 caps = 0; // Read ID_ISAR5_EL1
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// __asm __volatile("mrs %0, " "id_isar5_el1" : "=r" (caps));
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// #endif
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//
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// The following does not work well either. Its appears to be missing constants, and it does not detect
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// Aarch32 execution environments on Aarch64
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// http://community.arm.com/groups/android-community/blog/2014/10/10/runtime-detection-of-cpu-features-on-an-armv8-a-cpu
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//
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bool CRYPTOPP_SECTION_INIT g_ArmDetectionDone = false;
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bool CRYPTOPP_SECTION_INIT g_hasNEON = false, CRYPTOPP_SECTION_INIT g_hasPMULL = false, CRYPTOPP_SECTION_INIT g_hasCRC32 = false;
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bool CRYPTOPP_SECTION_INIT g_hasAES = false, CRYPTOPP_SECTION_INIT g_hasSHA1 = false, CRYPTOPP_SECTION_INIT g_hasSHA2 = false;
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word32 CRYPTOPP_SECTION_INIT g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
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extern bool CPU_TryNEON_ARM();
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extern bool CPU_TryAES_ARMV8();
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extern bool CPU_TrySHA1_ARMV8();
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extern bool CPU_TrySHA2_ARMV8();
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extern bool CPU_TryCRC32_ARMV8();
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extern bool CPU_TryPMULL_ARMV8();
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void DetectArmFeatures()
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{
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g_hasNEON = CPU_TryNEON_ARM();
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g_hasPMULL = CPU_TryPMULL_ARMV8();
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g_hasCRC32 = CPU_TryCRC32_ARMV8();
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g_hasAES = CPU_TryAES_ARMV8();
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g_hasSHA1 = CPU_TrySHA1_ARMV8();
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g_hasSHA2 = CPU_TrySHA2_ARMV8();
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g_ArmDetectionDone = true;
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}
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#endif
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NAMESPACE_END
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// ***************** C++ Static Initialization ********************
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ANONYMOUS_NAMESPACE_BEGIN
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struct InitializeCpu
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{
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InitializeCpu()
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{
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#if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
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CryptoPP::DetectX86Features();
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#elif CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64
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CryptoPP::DetectArmFeatures();
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#endif
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}
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};
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#if HAVE_GCC_INIT_PRIORITY
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const InitializeCpu s_init __attribute__ ((init_priority (CRYPTOPP_INIT_PRIORITY + 20))) = InitializeCpu();
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#elif HAVE_MSC_INIT_PRIORITY
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#pragma warning(disable: 4075)
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#pragma init_seg(".CRT$XCU-020")
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const InitializeCpu s_init;
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#pragma warning(default: 4075)
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#else
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const InitializeCpu& s_init = CryptoPP::Singleton<InitializeCpu>().Ref();
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#endif
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ANONYMOUS_NAMESPACE_END
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#endif // CRYPTOPP_IMPORTS
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