Wei's AESNI routines use ARMV8_Enc_Block, ARMV8_Enc_4_Blocks, ARMV8_Dec_Block, ARMV8_Dec_4_Blocks. They increased performance for ECB, CTR and CBC mode. Formerly ECB mode was rinning at 2.3 cpb. After the cut-over ECB dropped to 1.1 cpb.
passed: 128 deflates and inflates
passed: 128 zlib decompress and compress
default.cpp:69:2: runtime error: null pointer passed as argument 2, which is declared to never be null
/usr/include/x86_64-linux-gnu/bits/string3.h:53:71: runtime error: null pointer passed as argument 2, which is declared to never be null
Information Dispersal and Secret Sharing...
GCC117 is a Aarch64/ARM64 server with AMD's ARM chip and GCC 7.10. It looks like GCC is performing some std::string optimizations that generates a finding. We did not witness the finding on other platforms, like other Aarch64 devices and x86_64.
We will need to check if taking the address of element-0 is still approved way to get the non-const pointer to the elements
GCC117 is a Aarch64/ARM64 server powered by AMD's ARM chip. It runs GCC 7.10. It looks like GCC is performing some std::string optimizations that generates a finding. We have not witnessed the finding on other platforms
Reworked SHA class internals to align all the implementations. Formerly all hashes were software based, IterHashBase handled endian conversions, IterHashBase repeatedly called the single block SHA{N}::Transform. The rework added SHA{N}::HashMultipleBlocks, and the SHA classes attempt to always use it.
Now SHA{N}::Transform calls into SHA{N}_HashMultipleBlocks, which is a free standing function. An added wrinkle is hardware wants little endian data and software presents big endian data, so HashMultipleBlocks accepts a ByteOrder for the incoming data. Hardware based SHA{N}_HashMultipleBlocks can often perform the endian swap much easier by setting an EPI mask so it was profitable to defer to hardware when available.
The rework also removed the hacked-in pointers to implementations. The class now looks more like AES, GCM, etc.
Jeffrey Walton